Multi-core MIPS64 network processor specialist Cavium Networks plans to expand into the storage processor market. The fabless chip house expects to begin sampling the first chips from a new Octeon Multicore Storage Services Processor (SSP) line later this year.
The Octeon SSP line will include two separate models, the CN57xx and CN55xx. Both target fiber channel and Ethernet disk arrays, RAID controllers, multi-protocol switches, single-chip iSCSI adaptors, virtualization equipment, and NAS/SAN equipment, Cavium said.
The higher-end CN57xx chips will integrate between six and 12 Linux-friendly MIPS64 cores, each clocked from 600MHz to 1GHz. I/O and memory interfaces will include:
- 2x [4xSGMII or 1xXAUI] networking interfaces
- Two 4-lane or one 8-lane PCI Express interfaces
- ECC memory interface supporting one each 72- and 144-bit memories, two 72-bit parts, or a single 144-bit part
CN57xx function block diagram
(Click to enlarge)
The lower-end CN55xx models, meanwhile, will integrate two to six MIPS64 cores, also clocked from 600MHz to 1GHz. Interfaces will include:
- 8x SGMII or 1xXAUI + 4 SGMII networking interfaces
- Two 2-lane, one 4-lane, or one 8-lane PCI Express interfaces
- One 72-bit memory interface supporting ECC memory
CN55xx function block diagram
(Click to enlarge)
Both models will be available with a choice of on-chip peripheral set mixes:
- SSP — secure storage processor — includes RAID, encryption, compression, networking, TCP acceleration, and QoS
- SP — storage processor — includes RAID, compression, networking, TCP acceleration, and QoS
Along with the newly announced SP and SSP parts, Cavium's Octeon line currently comprises the following models:
- NSP — network service processor — includes encryption, reg-ex acceleration, de/compression, networking, TCP acceleration, QoS
- EXP — “extreme” processor — includes reg-ex acceleration, de/compression, networking, TCP acceleration, QoS
- SCP — secure communications processor — includes encryption, networking, TCP acceleration, QoS
- CP — communications processor — includes packet processing, TCP acceleration, and QoS
Aileen A. Arcilla, senior analyst at IDC, stated, “Storage infrastructure is going through significant changes that include data consolidation driven by regulatory compliance, I/O virtualization, storage archival on disk, and increasing storage access over Wide Area Networks. These changes are driving the need for intelligent processing, higher capacity, reliability, security, and data compression in next generation storage solutions.”
Syed Ali, CEO of Cavium, stated, “Cavium's SSP processor family enables [a] common architecture across a broad range of performance and capacity points.”
CN57xx parts (with 6-12 cores) will sample in Q3, followed in Q4 by CN55xx parts (with 2-6 cores). Evaluation boards will also be offered. Pricing will range from $60 to $600 in 10K quantities.
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