Freescale Semiconductor has outlined plans for a dual-core, low-power PowerPC-based SoC (system-on-chip), but has not yet committed to sample or ship dates. The MPC8641D will be built using 90nm SOI (silicon-on-insulator) technology, and will feature dual e600 PowerPC cores. It will target networking, telecom, military, storage, and pervasive computing applications.
According to Freescale, the MPC8641D will be its most powerful chip yet, with dual e600 cores each delivering “greater than 1.5GHz performance.” The chip will also integrate two 1MB L2 caches, dual AltiVec vector processing engines, a high-bandwidth integrated MPX bus (inter-core bus) capable of clock speeds up to 667MHz, a dual memory controller supporting DDR and DDR2, a RapidIO serial fabric interface (useful in Linux/AdvancedTCA systems), and four 10/100/1000 Ethernet MACs with protocol accelerators of various kinds.
Freescale says that in lower bandwidth applications, one core can be used to manage the data plane while the other handles the control plane. Alternatively, the cores can handle the transmit and receive directions, respectively, of the data plane.
In higher bandwidth applications, Freescale says, both cores can run the same operating system, offloading classification, security, QoS (quality of service) or other tasks to one or more networking coprocessors.
Advantages of a dual-core architecture, according to Freescale, include:
- Reduced board space
- Lower power consumption
- Faster inter-core communication, for messages and semaphores, than a PCI bus could offer
- Increased memory bandwidth, and decreased latency
- High-performance coherency: cores can share most recently cached data without accessing main memory
Other new chips built on 90nm SOI technology
Additionally, Freescale plans to offer a pin-compatible single-core version of the new dual-core chip. The MPC8641 will also be based on 90nm SOI technology, as will another new chip, the MPC7448, which will be a 1.5GHz successor to the popular MPC7447A, Freescale says.
Freescale will disclose architectural details of the dual-core MPC8641D at the Fall Processor Forum on Oct. 5 in San Jose, and at the network Systems Design Conference on Oct. 21, also in San Jose.
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