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Freescale debuts PowerQUICC III quartet

Sep 29, 2004 — by LinuxDevices Staff — from the LinuxDevices Archive
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Freescale has announced four new PowerPC SoCs (system-on-chips) expected to sample in Q2, 2005. Each will use 90nm process technology said to decrease power consumption at higher clock rates. The four new PowerQUICC III chips will target enterprise networking, telecom transmission and switching, 3G wireless infrastructure, storage, and high-end imaging.

According to Freescale, the four new PowerQUICC chips will feature e500 PowerPC cores supporting clock rates up to 1.33GHz (with 1.5GHz to follow). They will use 90nm SOI (silicon-on-insulator) copper interconnect process technology, said to enable lower power dissipation at higher clock rates than current PowerQUICC III chips, which are based on 130nm process technology.

The new SoCs will also integrate 512KB of 8-way associative L2 cache that can be configured as cache or SRAM, and a 64-bit DDR/DDR2 memory controller supporting DDR-333 and DDR2-533 (667 to follow).

The new SoCs will also integrate a hardware random number generator and security processing engine said to accelerate DES/3DES, AES, ARC-4, Kasumi, MD5, SHA1/2, RSA and Elliptic Curve processing, yielding “up to 1 Gbps throughput” for widely used commercial security protocols such as IPSec, SSL/TLS, and 3GPP, Freescale says.

The four new SoCs include:

  • MPC8548E — a networking/telecom processor with dual 32-bit PCI or 64-bit PCI-X, 4-bit Serial RapidIO fabric bus, and 4-bit PCI-Express (or single 8-bit PCI Express 1.0a), local bus IO interfaces, and four Gigabit Ethernet interfaces. An onboard security engine includes Kasumi algorithm acceleration, for security protocol processing in 2.5G and 3G wireless network infrastructure. Claimed to be the first integrated communications processor to comply with the Serial RapidIO Interconnect Specification, Revision 1.2, from the RapidIO Trade Association. Targets Ethernet-only communications processing applications such as enterprise networking, telecom transmission and switching, and 3G wireless basestations.
  • MPC8547E — a storage processor with integrated security acceleration, support for battery-backed 64-bit DDR1/2, 64-bit PCI-X, 8-bit PCI Express, and four Gigabit Ethernet interfaces. XOR acceleration enhances system performance by offloading the compute-intensive parity checks in RAID storage systems for small-medium business (SMB) and enterprise markets.
  • MPC8545E — an imaging processor with integrated security, dual 32-bit PCI/single 64-bit PCI, 4-bit PCI Express, and two Gigabit Ethernet interfaces. A double-precision floating point unit provides high-performance image processing.
  • MPC8543E — a general-purpose control processor with 256KB L2 cache, integrated security, 64-bit DDR1/2 scaling up to 400 MHz data rate, 32-bit PCI, 4-bit Serial RapidIO or 4-bit PCI Express, and two Gigabit Ethernet interfaces. With clock frequencies scaling from 800 MHz to 1 GHz, this cost-effective device targets general-purpose embedded control applications, such as robotics, discrete manufacturing, and process manufacturing control.

Availability

Initial samples of the MPC8548E, MPC8547E, MPC8545E, and MPC8543E processors are planned for Q2 2005.


 
This article was originally published on LinuxDevices and has been donated to the open source community by QuinStreet Inc. Please visit LinuxToday.com for up-to-date news and articles about Linux and open source.

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