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First dual-core SuperH chips announced

Apr 23, 2007 — by LinuxDevices Staff — from the LinuxDevices Archive
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Renesas is readying its first dual-core processors based on its 32-bit SuperH architecture. Expected to sample in July, the SH7205 and four SH7265 models are described as general-purpose SoCs (system-on-chip processors) with two 200MHz SH2A-FPU cores, together with “comprehensive” on-chip peripheral sets, including an AAC encoder in four SH7265 models.

The new Renesas chips are the highest-powered SuperH chips yet. The company is also at work on a quad-core SH-4 chip model, it said.


Renesas's SuperH Roadmap
(Click to enlarge)

Once shipping, Renesas's SH7205 and SH7265 will cost just over $20, and will target applications requiring high-speed real-time control and processing performance “equivalent to that of a DSP” (digital signal processor), the company said. Cited applications include consumer, industrial, car audio/navigation, and multimedia applications.

Interestingly, all four announced SH7265 models include encoding hardware for AAC (advanced audio coding), together with extended temperature operation down to -40 degrees Celsius. AAC is Apple's format of preference for iPod- and iTunes-related products, and is said to outperform MP3 when used at low bitrates (100Kbps or lower). Presumably, the chips will see use in some as-yet unimagined automotive application for which low-bitrate, high-quality audio recording is needed.


SH7205 (left) and SH7265 (right) diagrams
(Click each image to enlarge)

Other on-chip functions and peripheral controllers included on both the SH7205 and SH7265, as listed by the company, include:

  • USB v2.0 High-Speed (480-Mbps) specification interface
  • ATAPI interface
  • “Various I/O”
  • 2D graphic engine and a digital video input pin for graphic processing
  • WQVA-size (480×234-pixel) and QVA-size (320×240-pixel) analog RGB output pins
  • 5-channel multifunction timer unit (MTU) suitable for motor control systems
  • 2-channel CAN controller
  • 8-channel 10-bit A/D converter
  • 2-channel 8-bit D/A converter
  • Watchdog timer (WDT)
  • 14-channel DMAC with 2-dimensional addressing capability for speeding up video applications

Renesas said it decided to create dual-core chips because of challenges associated with developing finer manufacturing process nodes, such as increased leakage current and other physical limitations to further miniaturization of computer microelectronics. The dual-core chips can increase device performance through parallel execution of multiple software lines, it said. When clocked at 200MHz, each CPU reportedly delivered 480 MIPS (millions of instructions per second) in Dhrystone 1.1 benchmarking, and 400 MFLOPS (millions of floating point operations per second).

Additional touted features and benefits include:

  • Parallel execution of the same or different OSes, such as uClinux on one core and iTron on the other.
  • Internal bus system uses a “CPU-specific multi-layer structure… a 4-layer configuration provides two layers for CPU use and two for [DMA] use. This prevents time from being wasted while the bus is in use by the other CPU.”
  • Inter-core communication, status checking, and data exchange using shared memory
  • Customers can use currently available compiler, assembler, and linker products

Availability

The SH7205 and SH7265 are set to sample in July, priced from $21 to $23. Both clock to 200MHz; the SH7265 adds extended temperature operation and AAC encoder hardware, plus an optional SD memory card interface, IEBus interface, or both.


 
This article was originally published on LinuxDevices and has been donated to the open source community by QuinStreet Inc. Please visit LinuxToday.com for up-to-date news and articles about Linux and open source.

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